A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel cell has a readout circuit that includes at least an output field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a portion of a conventional CMOS imager 10. The illustrated imager 10 includes an array of pixels 20 connected to a column sample and hold circuit 42 by pixel output lines 32. The imager 10 also includes a row decoder and driver 40, column decoder 44, readout programmable gain amplifier (PGA) 50, an analog-to-digital converter (ADC) 55, an image processor 60 and a control circuit 70.
Under the control of the control circuit 70, row lines RL connected to a row of pixels 20 are selectively activated by the row decoder and driver 40. Each pixel 20 in the activated row outputs sequentially a reset Vrst and pixel signal Vsig, not necessarily in that order, on a corresponding pixel output line 32. The column sample and hold circuit 42 samples, holds and then outputs the reset Vrst and pixel signals Vsig to the amplifier 50 as selected by the column decoder 44. A differential signal (Vrst-Vsig) is produced by the amplifier 50. The differential signal is digitized by the analog-to-digital converter 55. The analog-to-digital converter 55 supplies the digitized pixel signals to the image processor 60, which forms a digital image output.
Thus, every pixel 20 in a row is readout and input into the column sample and hold circuit 42, and then each column is serially (or sequentially) readout from the sample and hold circuit 42 for further processing. An exemplary timing diagram of the pixel readout and serial column readout is illustrated in FIG. 2. As can be seen from FIG. 2, row processing time tr is equal to tp+tcr, where tp is the time to readout the reset Vrst and pixel signals Vsig from the pixel 20 and tcr is the column readout time (i.e., total time to readout each column in a serial manner). An imager's frame rate (the inverse of the time required to readout an entire array) is dependent upon the row processing time tr. It is desirable to improve an imager's frame rate. If tp is 6 μsecs and tcr is 42.67 μsecs (e.g., 2048 columns @ 48 Mhz), row processing time tr is 48.67 μsecs.
Accordingly, there is a desire to decrease row processing time so that an imager's frame rate can be improved.